A register set (hereinafter, referred to as ‘RS’) is general means for defining operation modes in a semiconductor memory device. RS is usually composed of mode register sets (MRS) and extended mode register sets (EMRS). The mode register sets and the extended mode register sets, which are applied to address pins along with mode register set commands, determine operation modes for a semiconductor memory device. Information about operation modes once determined is maintained until a semiconductor memory device is reprogrammed or power of the semiconductor memory device is cut off or interrupted.
The mode register sets are necessary for dynamic random access memories (DRAM) or static random access memories (SRAM), determining operation modes, such as burst type, burst length, column address strobe (CAS) signal latency (CL) and read latency (RL), before using a semiconductor memory device chip. The mode register sets can be performed under test modes for examining semiconductor memory chips by vendors or under the Joint Electron Device Engineering Council (JEDEC) standard providing operations modes by users.
In the meantime, for a Dual Data Rate 2 (DDR2) DRAM, the mode register set offers a mode register writing (MRW) operation to input mode information set in registers and a mode-register reading (MRR) operation to retrieve the mode information from the registers. In general, the mode-register reading operation is carried out as shown in FIG. 1.
FIG. 1 shows a timing sequence of a general mode-register reading operation for a semiconductor memory device.
Referring to FIG. 1, if a mode-register read command MRR_COMMAND is input to the semiconductor memory device, a mode-register reading period signal MRR_EN is generated which maintains a high level during a mode-register reading period. After a predetermined delay time subsequent to when a more-register reading operation began by the mode-register read command MRR_COMMAND, an enable signal AYP_ROUT is activated into a high level state. The enable signal AYP_ROUT is made from a column enable signal AYP that is used for generating a column selection signal (YI; not shown). If the enable signal AYP_ROUT is activated in a high level, control signals MRR_STB1 and MRR_STB2 are activated into high level states after a predetermined delay time. Here, the control signal MRR_STB1 activated into a high level state is provided to load data into a global input/output line from a mode register in the mode-register reading operation. The control signal MRR_STB2 is provided to drive a pipe latch for transferring data into a data output buffer from the global input/output line.
The timing sequence, as shown in FIG. 1, may correspond to a mode-register reading operation applicable to the DDR800 standard (tCK=2.5 ns) that supports a system set at a read latency of 6tCK, or the higher. As can be seen from FIG. 1, in a high frequency operation, such as at a data rate over that of the DDR800 (tCK=2.5 ns), it is necessary to set the read latency to at least longer than 5tCK in order to output data from the mode register. However, the read latency is reset at 3tCK by a reset command. Thus, in a situation when a reset command is input while the mode-register reading operation is running in at this high frequency, a malfunction can arise because the read latency for outputting data from the mode register cannot be assured in the least term that is 5tCK.